diff -ruN a/safertos/portable/003_GCC/032_Aurix/port.c b/portable/003_GCC/032_Aurix/port.c
--- a/portable/003_GCC/032_Aurix/port.c	2019-02-21 08:07:07.000000000 -0800
+++ b/portable/003_GCC/032_Aurix/port.c	2020-01-24 16:19:54.990492000 -0800
@@ -1040,7 +1040,7 @@
 
 			/* Set new priority. */
 			uxRegPCXI &= ~portPCXI_PCPN_MASK;
-			uxRegPCXI |= ( ( ( portUnsignedBaseType ) configSYSTEM_INTERRUPT_PRIORITY ) << portPCXI_PCPN_SHIFT );
+			uxRegPCXI |= ( ( ( ( portUnsignedBaseType ) configSYSTEM_INTERRUPT_PRIORITY) + uxCoreId) << portPCXI_PCPN_SHIFT );
 
 			/* Write back. */
 			_mtcr( CPU_PCXI, uxRegPCXI );
@@ -1478,7 +1478,7 @@
 				 * then, the RFE instruction will copy PCXI.PCPN into ICR.CCPN.
 				 */
 				uxRegPCXI = puxLowerCSA[ portCOMMON_CSA_PCXI ] & ~portPCXI_PCPN_MASK;
-				uxRegPCXI |= ( ( ( portUnsignedBaseType ) configSYSTEM_INTERRUPT_PRIORITY ) << portPCXI_PCPN_SHIFT );
+				uxRegPCXI |= ( ( ( ( portUnsignedBaseType ) configSYSTEM_INTERRUPT_PRIORITY) + uxCoreId) << portPCXI_PCPN_SHIFT );
 				puxLowerCSA[ portCOMMON_CSA_PCXI ] = uxRegPCXI;
 
 				/* MCDC Test Point: STD_IF "vSafeRTOSInterruptHandler" */
@@ -1729,9 +1729,14 @@
 KERNEL_FUNCTION static portBaseType prvCheckKernelConfiguration( void )
 {
 portBaseType xReturn;
+/* Retrieve the core ID. */
+portUnsignedBaseType uxCoreId = uxDeviceGetCoreId();
+  if (deviceMAX_CORES <= uxCoreId) {
+    return errBAD_HOOK_FUNCTION_ADDRESS;
+  }
 /* The linker defines a region covering the whole flash. */
-portUnsignedBaseType uxMinFlashAddr = portmpuFLASH_START_ADDRESS;
-portUnsignedBaseType uxMaxFlashAddr = ( portmpuFLASH_START_ADDRESS + configMEM_PFLASH_SIZE ) - 2UL;
+portUnsignedBaseType uxMinFlashAddr = portmpuFLASH_START_ADDRESS(uxCoreId);
+portUnsignedBaseType uxMaxFlashAddr = ( portmpuFLASH_START_ADDRESS(uxCoreId) + configMEM_PFLASH_SIZE ) - 2UL;
 
 	/* Perform the required checks. */
 	if( ulCPUClockHz < portCPU_CLOCK_HZ_MIN )
diff -ruN a/portable/003_GCC/032_Aurix/portmpu.c b/portable/003_GCC/032_Aurix/portmpu.c
--- a/portable/003_GCC/032_Aurix/portmpu.c	2019-02-21 07:34:14.000000000 -0800
+++ b/portable/003_GCC/032_Aurix/portmpu.c	2020-01-24 15:49:38.244713000 -0800
@@ -121,8 +121,8 @@
 		aulRegionPermissions[ portmpuUSER_REGISTER_SET ] = 0UL;
 
 		vDeviceMpuConfigureSystemCodeRegion( portmpuKERNEL_FLASH_CODE_REGION,
-											 portmpuFLASH_START_ADDRESS,
-											 ( portmpuFLASH_START_ADDRESS + configMEM_PFLASH_SIZE ),
+											 portmpuFLASH_START_ADDRESS(uxCoreId),
+											 ( portmpuFLASH_START_ADDRESS(uxCoreId) + configMEM_PFLASH_SIZE ),
 											 aulRegionPermissions );
 
 		/* Unprivileged (cached) code region.
@@ -134,7 +134,7 @@
 
 		vDeviceMpuConfigureSystemCodeRegion( portmpuUNPRIV_FLASH_CACHED_CODE_REGION,
 											 portmpuPRIV_CODE_END_ADDRESS,
-											 ( portmpuFLASH_START_ADDRESS + configMEM_PFLASH_SIZE ),
+											 ( portmpuFLASH_START_ADDRESS(uxCoreId) + configMEM_PFLASH_SIZE ),
 											 aulRegionPermissions );
 
 		/* Privileged (uncached) code region - this is used for the vector and trap tables.
@@ -145,8 +145,8 @@
 		aulRegionPermissions[ portmpuUSER_REGISTER_SET ] = 0UL;
 
 		vDeviceMpuConfigureSystemCodeRegion( portmpuPRIV_FLASH_UNCACHED_CODE_REGION,
-											 portmpuFLASH_UNCACHED_START_ADDRESS,
-											 ( portmpuFLASH_UNCACHED_START_ADDRESS + configMEM_PFLASH_SIZE ),
+											 portmpuFLASH_UNCACHED_START_ADDRESS(uxCoreId),
+											 ( portmpuFLASH_UNCACHED_START_ADDRESS(uxCoreId) + configMEM_PFLASH_SIZE ),
 											 aulRegionPermissions );
 
 		/* Configure MPU Read-only data regions.
@@ -158,8 +158,8 @@
 
 		/* Flash (cached) data region. */
 		vDeviceMpuConfigureSystemDataRegion( portmpuKERNEL_FLASH_DATA_REGION,
-											 portmpuFLASH_START_ADDRESS,
-											 ( portmpuFLASH_START_ADDRESS + configMEM_PFLASH_SIZE ),
+											 portmpuFLASH_START_ADDRESS(uxCoreId),
+											 ( portmpuFLASH_START_ADDRESS(uxCoreId) + configMEM_PFLASH_SIZE ),
 											 aulRegionPermissions );
 
 		/* Configure MPU Read/Write data regions.
diff -ruN a/portable/003_GCC/032_Aurix/portmpu.h b/portable/003_GCC/032_Aurix/portmpu.h
--- a/portable/003_GCC/032_Aurix/portmpu.h	2019-02-21 07:34:14.000000000 -0800
+++ b/portable/003_GCC/032_Aurix/portmpu.h	2020-01-24 15:48:53.516964000 -0800
@@ -45,8 +45,8 @@
 #define portmpuMPU_REG_ADDRESS_MASK					( 0xFFFFFFF8U )
 
 /* Memory segment addresses. */
-#define portmpuFLASH_START_ADDRESS					( 0x80000000UL )
-#define portmpuFLASH_UNCACHED_START_ADDRESS			( 0xA0000000UL )
+#define portmpuFLASH_START_ADDRESS(core)					(0x80000000UL)
+#define portmpuFLASH_UNCACHED_START_ADDRESS(core)					(0xA0000000UL)
 
 #define portmpuPERIPHERAL_START_ADDRESS				( 0xF0000000UL )
 #define portmpuPERIPHERAL_END_ADDRESS				( 0xFFFFFFFFUL )
